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The semiconductor industry has long grappled with one of its most persistent challenges – the extraordinary time and cost required to bring a new chip from concept to production. Tattvam AI, a deeptech startup co-founded by Bragadeesh Suresh Babu and Lannan Jiang, is positioning itself at the forefront of solving this problem. On February 25, 2026, the company announced the successful close of a $1.7 million pre seed funding round, marking a decisive first step in its journey to transform how chips are designed.
The Round and Its Backers
The investment was led by Seedcamp, with contributions from EWOR, Entropy Industrial Ventures, Concept Ventures, and Stan Boland – a respected figure in the semiconductor world and former founder and CEO of both Icera and Element 14. Boland’s involvement carries particular weight, given his hands on experience navigating the very complexities that Tattvam AI seeks to eliminate. The funds will be channelled into engineering recruitment, advancing research, preparing the company’s debut product for market, and cultivating relationships with prominent chip design organisations.
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Addressing a Long Standing Industry Bottleneck
Chip design today is a painstaking, multi year endeavour. Engineers must work within a demanding framework of Electronic Design Automation (EDA) tools, balancing cascading technical constraints with performance targets – a process that has resisted meaningful acceleration despite decades of progress in adjacent fields. Tattvam AI contends that conventional AI tools, including the latest generation of large language models, fall short because they lack the structural comprehension that circuit design fundamentally requires.
A New Kind of Reasoning Engine
Rather than adapting existing models for the task, Tattvam AI is constructing a specialised reasoning system that interprets circuit logic from the ground up accounting for component interdependencies, design tradeoffs, and performance constraints the way an experienced engineer would. The ambition is to reduce design cycles that currently span years down to a matter of weeks, enabling faster iteration and more targeted chip development for specific applications.
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